1. Field of the Invention
The invention generally relates to signal delay systems which are used to delay a signal for n period lengths and, more specifically, to signal delay systems which employ the use of shift registers requiring capacities which do not correspond to binary steps.
2. Description of the Prior Art
The use of shift registers to delay signals is well known. The delay time which can be achieved with a shift register is dependent on the frequency of the timing signal and the specific number of register elements of the shift register being used. Since the frequency of the timing signal is usually specified beforehand in general transmission systems, a set delay time can be realized only by a shift register with a corresponding number of register elements. However, moderately priced shift registers of integrated circuit designs are predominantly offered in shift register element numbers in binary steps (2.sup.n).